The present invention relates to semiconductor design technology, and more particularly to a nonvolatile memory device and a reading method thereof.
A NAND type flash memory device is one of nonvolatile memory devices. The NAND type flash memory device includes a plurality of unit strings, each having a plurality of cells connected in series for the high degree of integration. The NAND type flash memory is used in various fields, for example, memory sticks, universal serial bus (USB) drivers, and hard disks.
FIG. 1 a block diagram of a conventional NAND type flash memory device. FIG. 2 is a schematic circuit diagram of blocks BLK0 to BLK4095 illustrated in FIG. 1. FIG. 3 is a sectional view of blocks BLK0 to BLK4095 connected to a bit line BL0 illustrated in FIG. 2.
Referring to FIGS. 1 to 3, the conventional NAND type flash memory includes a plurality of bit lines BL0 to BLn, a plurality of word lines WL0 to WL31, and a memory cell array 100 comprising a plurality of strings. The bit lines BL0 to BLn are intersected with the word lines WL0 to WL31. Each of the strings includes a plurality of memory cells MC0 to MC31, a drain select transistor DST, and a source select transistor SST. The drain select transistor DST and the source select transistor SST are connected in series to the memory cells MC0 and MC31, respectively, to select the string. The drain select transistor DST is selected by a drain select line DSL, and the source select transistor SST is selected by a source select line SSL. Additionally, sources of the source select transistors SST in the respective strings are connected to a common source line CSL.
The NAND type flash memory device performs read and program operations on a page basis, and performs an erase operation on a block basis. Here, one page includes memory cells which have control gates commonly connected to one word line. A plurality of pages form a cell block and in each of the cell blocks BLK0 to BLK4095, one or a plurality of cell strings are connected to each bit line. Substantially, electron transition between a floating gate and a channel of a memory cell only occurs in a program operation and an erase operation. After the program and erase operations are completed, a read operation is performed just to read data from a memory cell without data loss.
In the read operation, a voltage applied to a control gate of an unselected memory cell is higher than a voltage applied to a control gate of a selected memory cell. A current may or may not flow through a corresponding bit line according to a threshold voltage of the selected memory cell. Under a predetermined voltage condition, when a threshold voltage of a programmed memory cell is higher than a reference voltage, the memory cell is read as an off-cell and a high level voltage is charged on a corresponding bit line. On the other hand, when a threshold voltage of a programmed memory cell is lower than a reference voltage, the memory cell is read as an on-cell and a corresponding bit line is discharged to a low potential level. The potential level on the bit line is finally read as ‘0’ or ‘1’ through a sense amplifier, called a page buffer 110.
In the conventional NAND type flash memory device, however, a plurality of cell blocks BLK0 to BLK4095 are allocated to one page buffer 110. In this case, a total number of cell strings connected to one bit line is 4096, and a total number of drain select contact plugs DCT connected to drains of the drain select transistors DST is 2048.
In general, most of a leakage current flowing through a bit line occurs in a path between the drain select contact plug DCT and the drain select transistor DST. In the case that 2048 drain select contact plugs DCT exist in one bit line, a total leakage current of the bit line increases accordingly. Therefore, in the page-based read operation, a leakage current due to the drain select contact plug DCT of the unselected memory cell block can greatly affect a corresponding bit line. Consequently, the bit line may be maintained in a discharged state due to the leakage current and a programmed cell may be determined as an erased cell.